1. Field of Invention
The inventive principles of this patent disclosure relates to a semiconductor memory device, and more particularly, to methods and apparatus in which redundancy fuse block arrays are arranged to accommodate testing of the memory device.
2. Description of the Related Art
Semiconductor memory devices have increasingly become faster and more highly integrated with the development of precision technology. In particular, semiconductor memory devices require high yields in addition to high integration. A semiconductor memory device includes numerous memory cells. Even a single defective memory cell can hinder the semiconductor memory device from operating properly.
As semiconductor memory devices become more highly integrated, memory cells included therein are more likely to be defective. Generally, defects are found in a small number of memory cells. Defective memory cells are a major cause of reduced yields since they interfere with the functions of semiconductor memory devices. Therefore, redundant circuit technology is widely used to increase yields in semiconductor memory devices. Redundant circuit technology enables detection and replacement of defective memory cells with spare (redundant) memory cells during testing to enhance yields of semiconductor memory devices.
In general, a redundancy circuit drives a redundancy memory cell block in which spare rows and columns of redundancy memory cells are arranged. The redundancy circuit selects a row or column of redundancy memory cells within the redundancy memory cell block to replace a row or column of memory cells having one or more defective memory cells. The redundancy circuit selects a row or column of redundancy memory cells in response to an address signal designating a row or column of memory cells including the defective memory cells. To this end, the redundancy circuit includes a fuse block array in which a plurality of fuses are arranged. The fuses are programmed such that fuses corresponding to a defective row address or defective column address are cut or burned to open the fuses.
FIG. 1 is a block diagram of a conventional memory device 100 including a plurality of redundancy fuse block arrays 151 through 158. Referring to FIG. 1, the memory device 100 includes an A bank 110, a B bank 120, a C bank 130, and a D bank 140. The A bank 110 and the B bank 120 have a stack bank structure for sharing a first row decoder 150. Alternatively, the A bank 110 and the B bank 120 may have a stack bank structure for sharing a column decoder (not shown). The A bank 110 and the B bank 120 memory cells are addressed using the shared row decoder 150 or the column decoder. The C bank 130 and the D bank 140 also have a stack bank structure for sharing a second row decoder 160.
The redundancy fuse block arrays 151 through 158 for repairing defective rows of the A bank 110 and the B bank 120 with redundancy rows are arranged in the first row decoder 150. The redundancy fuse block arrays 151 through 158 may be used to repair defective columns of the A bank 110 and the B bank 120 with redundancy columns.
The redundancy fuse block arrays 151 through 154 for the A bank 110 are arranged adjacent to the A bank 110, and the redundancy fuse block arrays 155 through 158 for the B bank 120 are arranged adjacent to the B bank 120. Similarly, redundancy fuse block arrays for the C bank 130 are arranged adjacent to the C bank 130, and redundancy fuse block arrays for the D bank 140 are arranged adjacent to the D bank 140 in the second row decoder 160.
When the memory device 100 is tested to repair defective rows, a tester programs the redundancy fuse block arrays 151 through 154 for the A bank 110 to replace defective rows of the A bank 110 with redundancy rows while moving in a first direction, for example, an X-axis direction, of the memory device 100. Then, the tester programs the redundancy fuse block arrays 155 through 158 for the B bank 120 to replace defective rows of the B bank 120 with redundancy rows while moving in a Y-axis direction and then the X-axis direction of the memory device 100.
If few defective rows are found in the A bank 110 or the B bank 120, then not all of the redundancy fuse block arrays 151 through 154 for the A bank 110 are required to repair defective rows of the A bank 110. Generally, one or two of the four redundancy fuse block arrays 151 through 154 for the A bank 110 are used to repair the defective rows of the A bank 110. Similarly, if few defective rows are found in the B bank 120, then not all of the redundancy fuse block arrays 155 through 158 for the B bank 120 are required to repair defective rows of the B bank 120.
However, the tester passes all the redundancy fuse block arrays 151 through 154 for the A bank 110 while moving in the X-axis direction of the memory device 100 to repair the defective rows of the A bank 110 and then passes all the redundancy fuse bock arrays 155 through 158 for the B bank 120 while moving in the Y-axis direction and then in the X-axis direction of the memory device 100 to repair the defective rows of the B bank 120.
Accordingly, even when there is no need to repair many defective rows of the A bank 110, the tester wastes time passing all of the redundancy fuse block arrays 151 through 154 for the A bank 110 included in the memory device 100. In addition, since the tester shifts from the X-axis direction, to the Y-axis direction, and then to the X-axis direction of the memory device 100, a longer test time is required.